Electronics & Telecommunication undergraduate student specializing in Digital ASIC Design, RTL Development, and RISC-V Microarchitecture with hands-on experience in Verilog/SystemVerilog, FPGA prototyping, and functional verification. Designed and implemented a 32-bit RISC-V processor on FPGA, along with high-performance pipelined accelerators. Strong foundation in datapath design, pipelining, timing analysis, and SoC-level integration. Seeking internship opportunities in Digital IC Design, RTL Design, and Verification Engineering